Nanotech 2002 Vol. 1
Nanotech 2002 Vol. 1
Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems

Compact Modeling Chapter 13

Challenges of Modeling VLSI Interconnects in the DSM Era

Authors: N.D. Arora

Affilation: Simplex Solutions, United States

Pages: 645 - 648

Keywords: interconnect parasitic extraction, interconnect modeling, silicon validation of interconnect models

As VLSI technology shrinks to deep sub-micron (DSM) geometries (below 0.18mm), the parasitic due to interconnects are becoming a limiting factor in determining circuit performance. An accurate modeling of interconnect parasitic resistance (R), capacitance (C) and inductance (L) is thus essential in determining various chip interconnect related issues such as delay, cross-talk, IR drop, power dissipation etc. Solutions that provide extreme accuracy, though suitable for very small design with few hundred of devices, become impracticable and unrealistic when applied to the full chip with millions of devices, a common place in today’s DSM era. In this paper we will review practical methods of accurately estimating R, C, and L of a given circuit layout that maximizes the accuracy while minimizing the time and resources that such accuracy demands. The paper then covers other related issues as model order reduction and silicon validation of the models.

Challenges of Modeling VLSI Interconnects in the DSM Era

ISBN: 0-9708275-7-1
Pages: 764