Compact Modeling of Tunneling Breakdown in PN Junctions for Computer-Aided ESD Design (CAD for ESD)

	Nanotech 2002 Vol. 1 Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems Chapter 12: Circuit Simulation
	Compact Modeling of Tunneling Breakdown in PN Junctions for Computer-Aided ESD Design (CAD for ESD)
Authors:	Y. Subramanian and R.B. Darling
Affilation:	University of Washington, US
Pages:	628 - 631
Keywords:	tunneling, compact modeling, ESD, CAD
Abstract:	This paper presents compact, physically-based electrothermal models for direct as well as indirect bandgap tunneling processes in pn-junctions for use in network simulators (e.g. Saber or VHDL-A). The model for indirect tunneling has been validated using a 3.3V Si Zener diode (1N4728). Self-heating effects have also been included. The above tunneling breakdown models, together with the compact models for avalanche breakdown presented previously[1] constitute a complete, compact representation of breakdown in ESD zener diodes. Their utility lies in the simulation of large systems of interconnected ESD structures, without detailed device analysis, permitting a 'CAD-for-ESD' approach in commercial ESD design.
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ISBN:	0-9708275-7-1
Pages:	764
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