 | Nanotech 2002 Vol. 1
Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Chapter 12: Circuit Simulation |
| - | Compact Thermal Model for Transient Temperature Fields in Electronic Systems |
| | Y.C. Gerstenmaier and G. Wachutka |
| | Munich University of Technology, Germany |
| - | An Algorithm for the Inclusion of RC Compact Models of Packages into Board Level Thermal Simulation Tools |
| | M. Rencz, V. Székely and B. Courtois |
| | TIMA-CMP, France |
| - | Physics-Based and Compact Models for Self-Heating in High-Speed Bipolar Integrated Circuits |
| | A. Pacelli, P. Palestri and M. Mastrapasqua |
| | State University of New York-Stony Brook, USA |
| - | Extraction of Coupled RLC Network from Multi-level Interconnects for Full Chip Simulation |
| | S. Yoon and T. Won |
| | Inha University, Korea |
| - | Simulation of Heterojunction Bipolar Transistor with Domain Decomposition Method |
| | Y. Zhang and P.P. Ruden |
| | Oklahoma State University, USA |
| - | Compact Modeling of Tunneling Breakdown in PN Junctions for Computer-Aided ESD Design (CAD for ESD) |
| | Y. Subramanian and R.B. Darling |
| | University of Washington, USA |
| - | Characterization of “Multipath Interconnects” for Microelectronic and Nanotechnology Circuits |
| | A.K. Goel and N.R. Eady |
| | Michigan Technological University, USA |
| - | Novel Computing Architecture on Arrays of Josephson Persistent Current Bits |
| | J. Han and P. Jonker |
| | Delft University of Technology, The Netherlands |
| - | The New Approach to the Power Semiconductor Devices Modelling |
| | L. Starzak, M. Zubert and A. Napieralski |
| | Technical University of Lodz, Poland |
| - | Compact Thermal Model for Transient Temperature Fields in Electronic Systems |
| | Y.C. Gerstenmaier and G. Wachutka |
| | Munich University of Technology, Germany |
| - | An Algorithm for the Inclusion of RC Compact Models of Packages into Board Level Thermal Simulation Tools |
| | M. Rencz, V. Székely and B. Courtois |
| | TIMA-CMP, France |
| - | Physics-Based and Compact Models for Self-Heating in High-Speed Bipolar Integrated Circuits |
| | A. Pacelli, P. Palestri and M. Mastrapasqua |
| | State University of New York-Stony Brook, USA |
| - | Extraction of Coupled RLC Network from Multi-level Interconnects for Full Chip Simulation |
| | S. Yoon and T. Won |
| | Inha University, Korea |
| - | Simulation of Heterojunction Bipolar Transistor with Domain Decomposition Method |
| | Y. Zhang and P.P. Ruden |
| | Oklahoma State University, USA |
| - | Compact Modeling of Tunneling Breakdown in PN Junctions for Computer-Aided ESD Design (CAD for ESD) |
| | Y. Subramanian and R.B. Darling |
| | University of Washington, USA |
| - | Characterization of “Multipath Interconnects” for Microelectronic and Nanotechnology Circuits |
| | A.K. Goel and N.R. Eady |
| | Michigan Technological University, USA |
| - | Novel Computing Architecture on Arrays of Josephson Persistent Current Bits |
| | J. Han and P. Jonker |
| | Delft University of Technology, The Netherlands |
| - | The New Approach to the Power Semiconductor Devices Modelling |
| | L. Starzak, M. Zubert and A. Napieralski |
| | Technical University of Lodz, Poland |
| ISBN: | 0-9708275-7-1 |
| Pages: | 764 |
| Hardcopy: | $100.00 |
| Special: | 3 CD Set — 15% off with Free Shipping |
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