Sipahi L.B., Sanders T.J.
Florida Institute of Technology, US
Keywords: cost, cycle time reduction in semiconductor IC manufacturing, LNA in wireless communications, modeling, RF, simulation, statistical design of ICs
In this study, an investigation into MOS (metal-oxide semiconductor) and bipolar LNAs (Low Noise Amplifiers) in terms of their circuit design and the electrical circuit parameters was conducted. As partially reported [1], we have been methodically investigating physics base modeling and statistical simulations of the bipolar LNAs in terms of their associated semiconductor device, and silicon processing parameters. Here we report the comparative analyses of the single-stage, common source n-channel enhancement MOS transistor and common emitter class A npn bipolar LNAs. These 2.4 GHz low noise amplifier circuits were studied in terms of their electrical circuit parameters such as NF (Noise Figure) and output gain. Then, their dependence on semiconductor device, and silicon processing parameters for both technologies were compared and discussed in detail. A feasibility of implementing the novel statistical approach methodology was further investigated.
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Published: April 22, 2002
Pages: 584 - 587
Industry sector: Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems
ISBN: 0-9708275-7-1