Nano Science and Technology Institute
Nanotech 2001 Vol. 1
Nanotech 2001 Vol. 1
Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems
Chapter 9: Process Modeling

Layout Verification and Correction of CMOS-MEMS Layouts

Authors:B. Baidya, K. He and T. Mukherjee
Affilation:Carnegie Mellon, US
Pages:426 - 429
Keywords:DRC, slotting, CMOS micromachining, micro-loading, slot hole shields, density requirement
Abstract:The advent of CMOS micromachining has introduced new design rules for fabrication of integrated CMOS-MEMS devices. This paper presents a context dependent DRC algorithm to handle the issues related to pre-fabrication verification of such layouts. In addition, problems related to density control, specific to CMOS-MEMS designs, are discussed. An automatic slotter which introduces MEMS-compatible slot holes is presented and its capability demonstrated. Having such verification and correction tools which address the needs of integrated CMOS-MEMS designs will help reduce inte-grated MEMS design time.
Layout Verification and Correction of CMOS-MEMS LayoutsView PDF of paper
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