Nanotech 2001 Vol. 1
Nanotech 2001 Vol. 1
Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems

Semiconductor Device Modeling and Novel Structures Simulation Chapter 10

Investigation of the Mechanism of Floating Node Assisted CMOS Latch-Up

Authors: S-P. Sim, P. Guo, A. Kordesch, W.F. Chen, C-M. Liu, C.Y. Yang and K. Lee

Affilation: Santa Clara University, United States

Pages: 526 - 529

Keywords: latch-up, floating node, TCAD, SCR, ESD

Abstract:
A new phenomenon of floating node assisted CMOS latch-up is experimentally observed and investigated using TCAD simulation. Using test structures having parasitic bipolar transistors and an electrically floating N+ diffusion node located at various distances from a power supply node, we observed clear snapback to a low impedance state when the floating node approaches within a few microns of the power supply node. Through TCAD simulation, we found that this floating node behaves like a virtual cathode of a PNPN structure when high enough field is sustained by the underlying high resistance well. Under this high field, the diffusion node is no longer electrically floating but virtually connected to the neighboring power node by avalanche breakdown. We conclude that floating diffusion nodes can enable latch-up, if located within a few microns of a power supply node.

Investigation of the Mechanism of Floating Node Assisted CMOS Latch-Up

ISBN: 0-9708275-0-4
Pages: 638