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 | Nanotech 2001 Vol. 1
Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems
Chapter 10: Semiconductor Device Modeling and Novel Structures Simulation |
| | Simulation of Recess-Structure Dependence of Gate-Lag Phenomena in GaAs MESFETs | | Authors: | K. Horio, Y. Mitani and A. Wakabayashi | | Affilation: | Shibaura Institute of Technology, Japan | | Pages: | 510 - 513 | | Keywords: | GaAs MESFET, gate lag, surface state, recessed gate, buried gate | | Abstract: | We have made two-dimensional simulation of turn-on characteristics of recessed-gate and buried-gate GaAs MESFETs, and studied how the gate-lag or the slow current transient (which may occur due to surface states) is affected by the recess-structural parameters and the off-state gate voltage VGoff . It is shown that when VGoff is around the threshold voltage (pinch-off voltage) Vth, the gate-lag could be greatly reduced by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when VGoff is much more negative than Vth. |  | View paper | | ISBN: | 0-9708275-0-4 |
| Pages: | 638 |
| Hardcopy: | $100.00 |
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