A Methodology for Modeling a Complex Geometry on Wafer from a Layout Data

	MSM 2000 Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems Chapter 9: Signal Integrity Simulation and Verification
	A Methodology for Modeling a Complex Geometry on Wafer from a Layout Data
Authors:	S. Yoon, O. Kwon and T. Won
Affilation:	Inha University, KR
Pages:	437 - 440
Keywords:	Interconnect, DRAM, Capacitance simulation, 3D FEM
Abstract:	This paper reports a novel methodology and its application to the modeling of a complex 3D geometry on wafer from a layout data. Our modeling method comprises the steps of: drawing a mask layout; transforming the mask layout into a 3D structure by simulating the physical semiconductor process; and extracting device parameters by numerical technique. In order to estimate a 3D structure from the mask layout data, we performed a topography simulation comprising various depositions and etching process steps. A finite element method (FEM) has been employed for extracting device parameters in the 3D structure such as a cell capacitor and interlayer dielectric. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 mm was chosen as a test vehicle to check the validity of the simulation. In this work, 62 parasitic capacitance with 4 cell-capacitance were extracted from a stacked DRAM cell structure over a bit line.
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ISBN:	0-9666135-7-0
Pages:	741
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