The 2.4F2 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM

	MSM 2000 Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems Chapter 8: Semiconductor Device Modeling
	The 2.4F2 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM
Authors:	M. Suzuki, T. Endoh, H. Sakuraba and F. Masuoka
Affilation:	Tohoku University, JP
Pages:	388 - 391
Keywords:	SGT, S-SGT, DRAM, three-dimensional memory
Abstract:	This paper reports that the Stacked-Surrounding Gate Transistor (S-SGT) DRAM achieves a cell size of 2.4F 2. The S-SGT DRAM is structured by stacking several SGT-type cells in series vertically. In order to realize cell size of 2.4F 2, we propose the cell design of S-SGT DRAM. By using proposed design, we demonstrate that the S-SGT DRAM can realize cell size of 2.4F 2 by process simulation, while cell size of conventional SGT DRAM is 4.8F 2. Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.
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ISBN:	0-9666135-7-0
Pages:	741
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