Nano Science and Technology Institute
MSM 2000
MSM 2000
Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems
Chapter 7: Compact Modeling for Deep Submicron Devices

Verilog-AMS Eases Mixed Mode Signal Simulation

Authors:I. Miller and T. Cassagnes
Affilation:Motorola ESD Europe, US
Pages:305 - 308
Keywords:spice, OVI, verilog, HDL, behavioral
Abstract:The ability to design and verify mixed mode (digital, analog, electrical, and non-electrical) systems is key to the development of new products for the ever expanding electromechanical market. Although there are several individual point tools that can address specific phases of the development flow, tools to make the total process more seamless and less disparate should start to appear at the start of this new millennium, fueled by the introduction of Verilog-AMS Hardware Description Languages(HDL) and other analog HDL languages. The Language Reference Manual (LRM) for Verilog-AMS, developed by and available from the Open Verilog International (OVI) group, forms the basis for the new Verilog-AMS language. The document describes the extensions to the IEEE standard digital simulation language Verilog that enable the description of analog and non- electrical behavior. The document soon to be made available to an IEEE standards organization has been going through the OVI standardization process since about 1995. Verilog-A simulators based on the OVI LRM 1.0 are currently available.
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