Compact Modeling for Deep Submicron Devices

	MSM 2000 Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems Chapter 7: Compact Modeling for Deep Submicron Devices
-	Verilog-AMS Eases Mixed Mode Signal Simulation
	I. Miller and T. Cassagnes
	Motorola ESD Europe, U.S.A.
-	A Novel Method for the De-Embedding of S-Parameters of Double Heterojunction d-doped PHEMTs - Modeling and Measurements
	R.V.V.V.J. Rao, J. Joe, Y.W.M. Chia, K.S. Ang, H. Wang and G.I. Ng
	National University of Singapore, Singapore
-	Modeling of On-Chip Simultaneous Swithcing Noise in VDSM CMOS Circuits
	K.T. Tang and E.G. Friedman
	University of Rochester, U.S.A.
-	Modeling of Threshold Voltage with Reverse Short Channel Effect
	K.Y. Lim, X. Zhou and Y. Wang
	Nanyang Technological University, Singapore
-	Behavioral Models and Specific Design Tool for New Power Integrated Devices
	T. Bordingnon, J.L. Sanchez, P. Austin and V. Houdbert
	LAAS/CNRS, France
-	Improved Prediction of Length/Temperature-Dependent Impact Ionization Induced Body Current Based on an Accurate Saturation Drain Voltage Model
	S.H.L. Seah, K.S. Yeo, J.G. Ma and M.A. Do
	Nanyang Technological University, Singapore
-	Analytical Results for the Current-Voltage Characteristics of an SOI-MOSFET
	H.C. Morris, E. Cumberbatch, T. Phillips and B. Hinderberger
	Claremont Graduate University, U.S.A.
-	A Novel Approach to Compact I-V Modeling for Deep-Submicron MOSFET's Technology Development and Circuit Simulation
	X. Zhou and K.Y. Lim
	Nanyang Technological University, Singapore
-	Automatic Generation of Equivalent Circuits from Device Simulation
	A. Pacelli, M. Mastrapasqua, M.A. Alam and S. Luryi
	Bell Laboratories, Lucent Technologies, U.S.A.
-	Genetic Algorithm Based MOSFET Model Parameter Extraction
	M. Keser and K. Joardar
	Motorola SPS, U.S.A.
-	A New Continuous Model for Deep Submicron MOSFETs
	K-M.S. Chan, N-C.A. Wong, C-J. Chao, D-B. Kao, S-C. Wong and C.Y. Yang
	Winbond Electronics Corporation America, U.S.A.
-	Mobility Degradation and Current Loss Due to Vertical Electric Field in Channel Area of Submicron MOS Devices
	A.A. Keshavarz, J.L. Walters and R. Sampson
	STMicrolectronics, U.S.A.
ISBN:	0-9666135-7-0
Pages:	741
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