Wafer Fabrication Process Simulation Including Cost: Which Should be Used in an In-Line Wafer Inspection Strategy, High Sensitivity and High Cost Inspection Machine or Low Sensitivity and Low Cost Inspection Machine?

	MSM 2000 Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems Chapter 17: Software Tools, CAD Systems
	Wafer Fabrication Process Simulation Including Cost: Which Should be Used in an In-Line Wafer Inspection Strategy, High Sensitivity and High Cost Inspection Machine or Low Sensitivity and Low Cost Inspection Machine?
Authors:	K. Nakamae, S. Yamaji and H. Fujioka
Affilation:	Osaka University, JP
Pages:	700 - 703
Keywords:	wafer fabrication, inspection process, remedy, sampling inspection, particle
Abstract:	By combing an event-driven simulation method including costs and a simple VLSI particle-induced yield predictor, we discuss that which should be used in an in-line wafer inspection strategy, a high sensitivity & high cost inspection machine or a low sensitivity & low cost inspection machine. Two segments of a DRAM fab line including the inspection and the defect sourcing stages are modeled. Simulated results show that setting an adequate wafer rejection condition and selecting a proper sampling plan obtain the minimum cost per chip regardless of the kind of inspection machine.
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ISBN:	0-9666135-7-0
Pages:	741
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