Applied Materials and A*Star's Institute of Microelectronics-SG, to Drive Advanced 3D Packaging with World-Class R&D Lab in Singapore
Joint R&D Centre is first dedicated facility of its kind focused on developing next-generation packaging technologies to feed the explosive growth of mobile devices
Story content courtesy of Applied Materials Newsroom, US and SG
The Centre of Excellence in Advanced Packaging has been built with a combined investment of over $100 million US from Applied Materials and IME-Singapore. The world-class facility features a 14,000 square foot Class-10 cleanroom and is equipped with a fully-integrated line of 300 millimeter manufacturing systems to support the research and development of 3D chip packaging, a critical growth area for the semiconductor industry. The Centre positions Singapore as a global leader in semiconductor R&D and is expected to help accelerate the development and adoption of 3D packaging technology globally.
Traditionally, chips are connected to packages using wires attached to only their edges. This approach limits the possible number of connections from the chip and the long wire connections result in signal speed delays and power inefficiencies. With 3D chip packaging, multiple chips can be stacked on top of each other and connected with wiring that runs vertically through the stack (TSVs). When used to stack memory chips on logic chips, this technology is expected to reduce package size by 35%, decrease power consumption by 50%, and increase data bandwidth by a factor of eight or more times.
Conceived to support research collaboration between Applied Materials and IME-Singapore, the Centre will also allow both parties to pursue independent research initiatives including process engineering, integration and hardware development.