University of Connecticut and Duke University Co-Develop Novel Screening Technique For Semiconductors
New methodology will detect SDDs and improve quality, reliability of semiconductor products
The research teams are using a much-reduced pattern count in the chip testing process to detect small delay defects (SDDs). “By evaluating each test pattern according to its unique paths before applying the patterns to silicon, it allows the industry to select only high-quality patterns for testing. This will help to dramatically improve the quality of the test process and reduce the delay test costs while testers budgets,” notes Mohammad Tehranipoor, associate professor of Electrical and Computer Engineering, University of Connecticut, and Krishnendu Chakrabarty, professor of Electrical and Computer Engineering, Duke University, in the press release. The team is looking to bring the technology to commercialization. The chip testing process is being evaluated on silicon at Advanced Micro Devices, Inc. (AMD). The research was supported by the Semiconductor Research Foundation (SRF) and the NSF.
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