Tapeout of a 65-nm Production Design Has Been Publicly Disclosed
Cadence Design Systems, Inc., announced that Silicon & Software Systems (S3), a design services provider, has completed tapeout of a 65-nanometer, 500-MHz computing device for consumers using the Cadence Encounter digital IC design platform. According to Cadence, the device will be manufactured in a European 65-nm silicon wafer fab and is expected to reach high production volumes. This announcement is significant for two reasons: it is the first public disclosure of a 65-nm tapeout, and that the tapeout does exist. Several leading IC manufacturers, including Intel Corp., have plans to start 65-nm production by the end of 2005.
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