NSTI Nanotech 2009

Compact Model Application to Statistical/Probabilistic Technology Variations

X. Zhou, G. Zhu, M. Srikanth, R. Selvakumar, Y. Yan, W. Chandra, J. Zhang, S. Lin, C. Wei, Z. Chen
Nanyang Technological University, SG

Keywords: predictive compact model, probabilistic CMOS, process fluctuation, sensitivity analysis, statistical variation


ULSI systems are designed by electronic design automation (EDA) tools with performance figures-of-merit (FOM) measured by SPICE circuit simulation, in which nonlinear transistors are modeled by the compact model (CM) with its nominal set of parameters extracted from a golden die of the given technology. Inevitable technology variations are represented by parameter statistical distributions, from which process corners and variations are checked by Monte Carlo simulations within the design margins. In this paper, we examine CM application to statistical and probabilistic technology variations based on the predictive and non-binnable model with minimal physically meaningful parameters. To capture geometry variations physically, a binned model with too many empirical fitting parameters can never provide physically meaningful statistics. Statistics and probability theories are applied to the mathematical CM for describing major transistor FOM’s and their bias, geometry, and process variations as well as functional parameter sensitivities. Propagation of model statistics and variations to higher-level primitives (such as logic gates) and its application to probabilistic CMOS design paradigms is explored.
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