NSTI Nanotech 2009

Compact Modeling of Dynamic Threshold Voltage of FinFET High K Gate Stack and Application in Circuit Simulation

F. He, C. Ma, B. Li, L. Zhang, X. Zhang, X. Lin
SZPKU, CN

Keywords: FinFET, dynamic threshold voltage, device physics, compact modeling

Abstract:

Compact modeling study of dynamic threshold voltage of FinFET high K gate stack is proposed in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of Id is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.
 
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