NSTI Nanotech 2009

RF Modeling of 45nm Low-Power CMOS Technology

J. Wang, H. Li, L-H Pan, U. Gogineni, R. Groves, B. Jagannathan, M-H Na, W. Tonti, R. Wachnik
IBM Semiconductor Research and Development Center, US

Keywords: RF modeling, MOSFET, deembedding, RFCMOS, wiring capacitance

Abstract:

As CMOS has grown to be one of the principle technologies for RF IC design, accurate modeling of MOSFETs at high frequencies becomes increasingly important. In this paper, we present an advanced RF modeling work for our state-of-the-art 45nm low-power CMOS technology. Based on carefully designed structures, we extracted a rigorous hardware-based wiring capacitance (wirecap) model that accurately computes each component of the wirecap network on top of the intrinsic FET. A novel, scalable substrate resistance model was created to well fit relevant hardware data. To obtain accurate on-wafer s-parameter data for the modeling structures at high frequencies (up to 110GHz), we adopted sophisticated deembedding techniques (e.g., Pad-Open-Short and COMPLETE), instead of using the industry-standard Open-Short approach, which had been proven to cause errors when Freq.>30GHz. The results clearly show that our models well match various RF characteristics for devices with a broad range of sizes and measured at different voltage biases. Undoubtedly, these high-quality RF FET models offer circuit designers an indispensable and powerful tool to best utilize our advanced RFCMOS technology.
 
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