NSTI Nanotech 2009

Embedded non–volatile memory study with surface potential based model

D. Garetto, A. Zaka, V. Quenette, D. Rideau, E. Dornel, W.F. Clark, M. Minondo, C. Tavernier, Q. Rafhay, R. Clerc, A. Schmid, Y. Leblebici, H. Jaouen
STMicroelectronics, FR

Keywords: embedded non-volatile memory, surface potential compact model, short channel effects, saturation velocity, overlap capacitance

Abstract:

Coupling coefficients calculation is known to be a critical issue in Non-Volatile Memory cell compact modelling. To this purpose, the accuracy of the capacitive network method can be significantly improved using the charge balance method, both methods relying on the floating gate potential calculation. In this study, the charge balance method has been implemented in a surface potential based model accounting for short channel and saturation velocity effects on both currents and charges, including an advanced 3-terminals-overlap model and fringing capacitances. The results obtained by our semi-analytical model are compared to 2D TCAD simulations, which have been previously calibrated on 65nm-node measurements. Excellent agreement is found for various device lengths and bias conditions. It is shown that the short channel effects, overlap capacitances and velocity saturation dominate over the intrinsic behaviour of the cell in ultra scaled devices, each playing an independent role on the coupling coefficients. Showing the dependency of the drain current with respect to stored FG charge, we extended our research to transient analysis, demonstrating the capability of our model to simulate the full electrical behaviour of a flash cell.
 
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