2008 NSTI Nanotechnology Conference and Trade Show - Nanotech 2008 - 11th Annual

Partnering Events:

TechConnect Summit
Clean Technology 2008

Modeling of Spatial Correlations in Process, Device, and Circuit Variations

N. Lu
IBM, US

Keywords:
statistical models, compact models, SPICE models, process variations, spatial correlations

Abstract:
We present an innovative method to model the spatial correlations in semiconductor process and device variations or in VLSI circuit variations. Without using the commonly adopted PCA approach, we give a very compact expression to represent a given spatial correlations among a set of similar statistical variables/instances located at different places on a chip/die. Our compact expression is easy for implementation in a SPICE model and is efficient in circuit simulations. In semiconductor processes and devices as well as in logic circuits, the degree of correlation between any two intra-die instances of a process/device/ circuit decreases with increasing separation between them. Various measured hardware data has revealed such a gradual de-correlation of spatial correlation over distance. Describing intra-die variations using spatial (i.e., distance-dependent) correlations unifies various descriptions of intra-die variations, such as mismatch, across chip variations, random uncorrelated variations, and random correlated variations, etc.


Nanotech 2008 Conference Program Abstract