An FPGA Architecture Using Vertical Silicon Nanowire Transistors
A. Bindal, D. Wickramaratne, S. Hamedi-Hagh
San Jose State University, US
nanowire transistors, nano-architecture, FPGA
This study presents an FPGA architecture using vertical silicon nanowire transistors. A complete picture from designing ultra low-power silicon nanowire transistors to their use in an FPGA architecture is given. Post-layout, worst-case rise delay changes with TR = 9FO + 61 in ps where FO corresponds to cluster fan-out; the fall delay similarly changes with TF = 12.5FO + 59.5 in ps. Average dynamic power dissipation measured at 10GHz is 3.1µW for a 4-LUT and 10.2µW for a cluster. A single 4-LUT occupies in the neighborhood of 2.6µm2 layout area. The total layout area of an FPGA cluster measures approximately 8.0µm2.
Nanotech 2008 Conference Program Abstract