Simulation of Field-Plate Effects on Lag and Current Collapse in GaN-based FETs
K. Itagaki, A. Nakajima, K. Horio
Shibaura Institute of Technology, JP
GaN, FET, field plate, current collapse, trap
Two-dimensional transient analyses of field-plate GaN MESFETs and AlGaN/GaN HEMTs with a semi-insulating buffer layer have been performed in which a deep donor and a deep acceptor are considered in the buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that drain lag is reduced by introducing a field plate because trapping effects become smaller. It is also shown that the current collapse and gate lag are also reduced in the field-plate structure. It is suggested that there is an optimum thickness of SiN passivation layer to minimize the buffer-related current collapse and drain lag in GaN-based FETs.
Nanotech 2008 Conference Program Abstract