A Low Cost Method for “Depositing” CNT based Interconnect
T. Mangir, J. Chaves, S. Chaves, M. Khairatkar
CNT, nano-electronics, interconnect, patterning
In this paper we will present the results of a techniques we have developed patterning CNT based interconnect for future nanoelectronics. Our techniques include a special patented (pending) way to develop a colloidal solution of CNTs so that a simple method can be used to “deposit” nano scale interconnects. This “programmable” method allows us to deposit any pattern on the wafers. We will present the method, and results of our tests and improvements on this technique to make it feasible for large scale use such as a device process line. We will also describe different base materials for this process. The results of this work brings a very significant and innovative development in moving this area forward.
Nanotech 2008 Conference Program Abstract