Modeling of FET Flicker Noise and Impact of Technology Scaling
C.-Y. Chen, Y. Liu, S. Cao, R. Dutton, J. Sato-Iwanaga, A. Inoue and H. Sorada
Stanford University, US
TCAD, flicker noise, charge trap, FETs
Ongoing scaling of device dimensions, including the introduction of new channel materials and device structures, as well as the incorporation of novel gate-stack materials, has major implications on noise performance metrics. In particular, flicker noise is intrinsically related to the interface properties and expected to be impacted by those new technology choices. This paper is aimed to address fundamental issues of flicker noise, including technology dependencies, with developed advanced TCAD capabilities. The implication of these simulations is also projected in terms of compact models. From TCAD perspective, the device-level numerical analysis of flicker noise in FETs is achieved by implementing the Impedance Field Method and tunneling-based non-local charge trapping/de-trapping. This physical approach is capable of simulating flicker noise in regimes both at sub-threshold and above threshold. Detailed numerical analysis is conducted for both high-k devices with hafnium-based gate dielectrics and hetero-structure MOS transistors incorporating buried SiGe channels. The effects of trap energetic/spatial distribution, non-uniform channel doping and hetero-structures are investigated. In addition, the TCAD modeling provides insight into the improvement of flicker noise compact models for devices in advanced technologies.
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Nanotech 2007 Conference Program Abstract