2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

A Setup for Automatic MOSFET Mismatch Characterization under a Wide Bias Range

H. Klimach, C. Galup-Montoro and M.C. Schneider
Federal University of Santa Catarina, BR

Keywords:
mismatch, test chip, electrical characterization, test structure

Abstract:
Mismatch is the denomination of time-independent variations between identically designed components. In analog circuits, the spread in the dc characteristics of supposedly matched transistors results in inaccurate or even anomalous circuit behavior. Also, for digital circuits, transistor mismatch leads to propagation delays whose spread can be of the order of several gate delays for deep-submicron technologies. The stochastic nature of the local mismatch of MOS transistors makes their electrical characterization a very complex task. A large number of samples, having different geometries, must be measured under a wide range of bias conditions, in order to characterize device behavior and extract statistical model parameters. In this paper we describe a low-cost MOSFET mismatch characterization setup. It is mainly composed of a test chip that contains 648 pairs of transistors for dc mismatch measurement, where the device selection hardware is placed inside the chip through the use of analog CMOS switches and a serial loading register. This circuit was successfully fabricated and characterized in the TSMC 0.35 um and in the TSMC 0.18 um bulk technologies.

Back to Program

Sessions Sunday Monday Tuesday Wednesday Thursday Authors Keywords

Nanotech 2007 Conference Program Abstract

 
 

Names, and logos of other organizations are the property of those organizations and not of NSTI.
This event is not open to the general public and NSTI reserves the right to refuse admission and participation to any individual.