2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

An Integrated High-Voltage PMOS Model for Power Simulation and Efficiency Prediction

J. Hall, Z. Luo and D. Connerney
Fairchild Semiconductor, US

Keywords:
high-voltage, MOS, model, power, efficiency, BSIM, parasitic

Abstract:
The standard BSIM3v3 model contains internal source-body and drain-body diodes which are sufficient for capacitance calculations and give an indication when the junctions become reverse-biased. In high-voltage/high-current applications, these junctions are now become a critical part of the circuit and need to be modeled much more “physically”. In a boost converter application, a high-voltage PMOS is connected with a separate source and bulk for short-circuit protection. This leads to a situation where the lateral PNP (drain-bulk-source) turns on and current flows from source to drain when the gate is turning “off”. Also, the VPNP from drain-bulk-substrate also can turn on when the PMOS is turning on which could lead to power loss. The BSIM model (or any other standard MOS model for that matter) does not account for these behaviors. A high-voltage PMOS model was developed that contains the extracted lateral (D-B-S) and vertical (D-B-Sub, S-B-Sub) bipolar junctions as well as other parasitic elements. This model was able to correctly predict the efficiency of a boost converter (where the standard BSIM model could not) as well as allow the designer to look at the trade-offs of the various parasitic current losses (lateral vs. vertical) which contribute to efficiency loss.

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