2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

Bonding Pad with Reduced Capacity

I. Mats and V. Tarcenco
Select Techno-Fix Ltd, CA

Keywords:
bonding, JFET, packaging, capacitance

Abstract:
The technical solutions for the Integrated Circuits (ICs) packaging remains enough conservative during microelectronics development. The ICs with active components having size of micrometers or even nanometers continue to have bonding pads area within hundreds square micrometers. The leads from the contact pads on a silicon substrate to the terminals in its package are bonded creating a parasitic capacitor. This process is one of the most critical steps that influence the reliability of the High Frequency (HF) Junction Field Effect Transistors (JFETs). We developed a bonding pad design, with parasitic capacity determined by contacting spot between the wire and bonding pad metallizing only. The proposed solution allows decreasing the gate-draining capacity in the pair of JFETs from 1.15 – 1.2 pF to 1.0 – 1.05 pF. We have supplied JFETs having bonding pads, with this technique, for wideband (0-500) MHz oscilloscopes

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