Compact Capacitance Model of LDMOS for Circuit Simulation
Y. Ma, P. Chen, H. Liang, J. Ma, M-C Jeng and Z. Liu
Cadence Design Systems, Inc., US
capacitance model, LDMOS, Cgd
Capacitance modeling in LDMOS is much more complicated than that in bulk MOSFET’s due to the fact of non-uniform lateral channel doping, the extended gate drain overlap region and its interaction with channel charges. Measurements show Cgd dropping after Vgs increases beyond a threshold point, which is different from the bulk MOSFET behavior. This can be explained by the RC network effect in capacitance measurement and verified using AC analysis in simulation.
One particular modeling issue in LDMOS is its channel charge due to non-uniform lateral channel doping, which results in non-uniform inversion charge density in the channel region even when the drain voltage is zero.
Special consideration is also needed to model the overlap region between the gate and the drain due to unique LDMOS structure. This part of the device is in general a p-type ( for n-type LDMOS ) device operated in the accumulation region under normal bias conditions. Since this region is also strongly influenced by the gate, it also contributes to the overall drain current behavior.
Another issue pertinent to LDMOS capacitance modeling is the distributed RC network effect. The measured value of Cgd in LDMOS is actually an effective value from Cgd, Cgc, and Cgs modulated by the resistance network including Rs, Rd, Rchannel and Rdrift. The drop of Cgd observed in the measurement is believed to be mainly due to this effect. This RC network effect, however, is not important in bulk MOSFET’s because of the cancellation of RC network effect due to symmetry of the device structure and the lack of Rdrift.
Those effects are properly handled in Cadence developed LDMOS model, and the model is validated with measurement data from different technologies.
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Nanotech 2006 Conference Program Abstract