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A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects

M.J. Kumar, V. Venkataraman and S.K. Gupta
Indian Institute of Technology, IN

Keywords:
high-K gate dielectric, threshold voltage, fringe capacitance, SOI MOSFET

Abstract:
In this paper, we propose a novel device structure, known as the Grounded Laminated Gate (GLG) SOI MOSFET to eliminate the gate fringe field effects on the threshold voltage of short channel SOI MOSFETs. Our simulaton results demonstrate that the threshold voltage roll-off with increasing dielectric constant is effectively elminated in the proposed structure.

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