Nanotechnology Conference and Trade Show - Nanotech 2006
> Program > Technical Conferences > Business & Development > Nano Impact Workshop > Nanotech Job Fair > Expo
Program
Sessions
Sunday
Monday
Tuesday
Wednesday
Thursday
Index of Authors
Index of Keywords
Confirmed Speakers
Conferences & Symposia

Conference Proceedings

Conference Technical Proceedings

Static Analog Design Methodology

F. Guigues, F. Rudolff and E. Kussener
L2MP UMR 6137 CNRS - ISEN-Toulon, FR

Keywords:
analog design methodology, EKV MOS model, ultra low power, weak, moderate and strong inversion, MOS sizing

Abstract:
When strong constraints of supply voltage (< 1V ) and bias current (< 100nA) are required, the only way to meet design’s
specifications without using huge silicon area consists on decreasing transistor’s inversion level and therefore going in moderate
inversion. Gm/Id methodology is a good solution in case of dynamic target, but unusable for static circuits. In this case, analog
designers need continuous over inversion level, hand calculation usable equations.
EKV 2.0 MOS model proposes current drain formula continuous from weak to strong inversion. This equation is invertible
and thus usable for hand calculation, but only when transistors are saturated. The solution proposed to have a conduction drain
current expression, continuous from weak to strong inversion and invertible, is to fix a conduction level .
Starting from proposed equations, or standard asymptotes when strong constraint of weak/strong inversion are imposed,
design’s equations can be found. On the other hand, design’s specifications such as acceptable transistors’ sizes or current
bias, permit to fix vectors of solutions for each design’s unknowns. Integration of these vectors and designs’ equations into a
mathematical computing software result in the creation of wholes of solutions which describe completely the design.
It is thus possible to made a complete study of a static circuit, independent of inversion level so as to make optimum
design. Supply voltage and silicium area can be unambiguously optimize, without risk of running in circle as in ”traditional”
approaches. Furthermore, it permits to use circuit simulator only for ”final polish”. As a consequence, the study made, changing
of technology can be made almost immediately.

Back to Program

Sessions Sunday Monday Tuesday Wednesday Thursday Authors

Nanotech 2006 Conference Program Abstract

 
Nanotechnology Conference | Terms of use | Privacy policy | Contact | NSTI Home
Program | Technical Conferences | Business & Development | Nano Impact Workshop | Nanotech Job Fair | Expo |
Nanotech 2006 Home | Press Room | Venue | Subscribe | Site Map
Names, and logos of other organizations are the property of those organizations and not of NSTI.
This event is not open to the general public and NSTI reserves the right to refuse admission and participation to any individual.