CMOS Compatability of Carbon Nanotubes on SOI Devices
M.S. Haque, S.P. Oei, K.B.K. Teo, F. Udrea, J.W. Gardner and W.I. Milne
Cambridge University Engineering Department, UK
MWCNTs, Silicon on Insulator, MOSFET, CVD, PECVD
This paper reports for the first time PECVD and CVD growth of MWNTs both aligned and non aligned on high temperature partially depleted CMOS SOI substrates. We also report for the first time the growth of Carbon Nanotubes on SOI ultra-thin membranes with the use of different catalysts (Fe, Ni) and optimized for vertically aligned and non aligned growth. Basic characterisation using Raman (G peak at 1593cm-1 and the D peak at 1400cm-1) and SEM pictures showed evidence of the presence of MWNTs both aligned and non – aligned on the SOI substrates and membranes. The SOI substrates, featuring CMOS devices and full IC, were subsequently tested to check the electrical performance after the high temperature growth. These particular wafers also contained some advanced high power devices and their functionality has been found to be virtually unchanged after CNT growth which proves that the CNT growth is fully compatible with CMOS SOI and the membrane technology. It is worth noting that standard bulk CMOS technology based on Aluminum metallization is not compatible with the post-CMOS growth of CNTs due to the low melting point of Al. In contrast, high temperature SOI using Tungsten as an interconnect metal is therfore well suited.
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Nanotech 2006 Conference Program Abstract