Numerical Simulation of Drain-Current Transients and Current Compression in GaN MESFETs
H. Takayanagi, K. Itagaki and K. Horio
Shibaura Institute of Technology, JP
GaN MESFET, trap, current compression, device simulation
Two-dimensional transient analyses of GaN metal-semiconductor field effect transistors (MESFETs) are performed in which a three level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are included. Quasi-pulsed current-voltage (I-V) curves are derived from the transient characteristics and are compared with steady-state I-V curves. It is shown that when the drain voltage VD is raised abruptly, the drain current ID overshoots the steady-state value, and when VD is lowered abruptly, ID remains at a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes quantitatively. The drain lag could be a major cause of current compression, although some gate lag is also seen due to the buffer layer. The current compression is shown to be more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the change of ionized deep-donor density becomes larger and hence the trapping effects become more significant. It is suggested that to minimize the current compression in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behavior may be degraded.
Back to Program
Nanotech 2006 Conference Program Abstract