A Circuit-Compatible Model for Ballistic Silicon Nanowire Transistors
Agere Systems, US
nanowire, circuit-compatible model
Silicon nanowire transistors (SNWT) are being extensively explored as a successor to CMOS. Silicon nanowires with a diameter as small as 2nm and having high carrier mobility have been achieved. Such developments shed light on the potential use of silicon nanowire transistors in future integrated circuits. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit level simulations become increasingly important.
In the past, surface-potential-based models by self-consistently solving the electrostatic potential and the charge distribution have been developed to assess SNWT performance. The starting point of such a model is the top of the barrier potential. Such a model provides accurate numerical computation and is flexible in terms of the device parameters. However, such a model is not easy-to-use form a circuit design point of view. The self-consistent loop to solve the barrier potential and the numerical calculation of the quantum capacitance make it impossible to incorporate the model into a SPICE-type circuit simulator.
For efficient circuit-level simulations, it is desirable to express device characteristics in terms of transistor terminal voltages and to model device current and quantum capacitance as closed or quasi-closed analytical forms. In this paper we describe techniques to construct a circuit-compatible silicon nanowire transistor model. Such techniques break the loop for calculating the surface potential and enable analytical formulations describing device performance (including the quantum charge, quantum capacitance as well as drain current) to be obtained as closed-form analytical functions in terms of the transistor bias voltages of VGS and VDS. Such a SNWT model is easy-to-use and makes circuit simulations possible.
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Nanotech 2006 Conference Program Abstract