Carrier Generation and Recombination Currents At Interface Traps in Surface-Potential-Based MOS Transistor Compact Models
C-T Sah and B.B. Jie
University of Florida, US
interface traps, generation-recombination-trapping, surface potential compact model, diagnostic tool, long-term reliability
Operation lifetime of logic MOS transistors, endurance of memory MOS transistors, noise in analog and RF MOS transistors, and power dissipation in all of these transistors, have their common origin in electron-hole generation-recombination-trapping (GRT) at the SiO2/Si interface traps. These effects become increasingly important as the transistor is scaled down for higher function density and performance. Thus, the GRT mechanisms and currents need to be added as an intrinsic component to the MOS transistors core model to supplement the drift and diffusion currents, starting with the long-wide channel baseline model. This paper shows that GRT currents can be easily added to all the surface-potential-based MOS transistor compact models. In addition, the powerful diagnostic tool using the dc steady-state recombination current measured in the base-terminal (R-DCIV), by forward-biasing one of the p/n junctions inheritent in the MOS transistor structure, is simultaneously implemented in the compact models. The original device and material parameters (including channel and overlap lengths and spatial variations of oxide thickness and impurity concentration in these regions) can then be extracted from the R-DCIV measurements which in turn can be used in the compact models not only for diagnostics of the design and manufacturing, but also for monitoring and optimizing long-term reliability and endurance via quantitative kinetic models and analyses.
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Nanotech 2006 Conference Program Abstract