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Symposium on

Nanoelectronics: Devices, Molecules, and Wires

Symposium Sponsor:  freescale semiconductor
Symposium Chairs:  Alex Demkov, Freescale Semiconductor, Inc.
 David K. Ferry, Arizona State University

Confirmed Speakers

Robert Chau Emerging Nanoelectronic Devices and their Benchmarking Methodology
Robert Chau, Intel Corporation, US (speaker biography)
Lars Samuelson Semiconductor Nanowires for Future Nanoelectronics
Lars Samuelson, Lund University, SE
Phaedon Avouris Electronics and Optoelectronics with Single Carbon Nanotubes
Phaedon Avouris, IBM, US
Spin Manipulation in Semiconductors and Spintronic Ultrafast Nanodevices
Alexander M. Bratkovsky, Hewlett-Packard Laboratories, US

Symposium Program

 

Tuesday May 10

10:30 Nano Scale Electronics ProcessingSalon 3
 Session chair: Doug Resnick, Molecular Imprints, US
10:30 Nano Scale Electronics Processing - Overview
D. Resnick, Molecular Imprints, US
11:00 Dip Pen Nanolithography: Towards Industrial Nanoscale Processing
J. Fragala, NanoInk, Inc., US
 
1:30 Nano Scale Electronics ProcessingSalon 3
 Session chair: Doug Resnick, Molecular Imprints, US
1:30 Resolution Enhancement in Nanoimprinting by Surface Energy Engineering
G.Y. Jung, W. Wu, Z. Li, S.Y. Wang, W.M. Tong and R.S. Williams, Hewlett Packard Laboratories, US
1:50 Wafer Scale Aligned Sub-25nm Metal Nanowires on Silicon (110) using PEDAL Lift-off Process
S.R. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson and P.D. Franzon, North Carolina State University, US
2:10 Self-Assembled Cluster Nanostructures and Nanodevices
S.A. Brown, J. Partridge, S. Scott, R. Reichel, A. Ayesh and K.C. Tee, Nano Cluster Devices Ltd, NZ
2:30 An Additive Soft-Lithography for Sub-Micron Patterning of Polydimethylsiloxane (PDMS) Resists on Electronic Materials
H. Ahn, K.J. Lee, W.R. Childs, A. Shim and R.G. Nuzzo, University of Illinois at Urbana-Champaign, US
2:50 Aspect Ratio Improvement using the 2-step NERIME FIB Top Surface Imaging Process for Nano-lithography Applications
K. Arshak, S.F. Gilmartin, D. Collins, O. Korostynska and A. Arshak, University of Limerick and Analog Devices, IE
 
4:00 NEMS and MEMS FabricationSalon 3
 Session chair: Doug Resnick, Molecular Imprints, US
4:00 Wafer Scale Fabrication of Nano Probes for Atomic Force Microscopy
Q.L. Ye, H. Liu, A.M. Cassell, K-J Chao and J. Han, NASA Ames Research Center, US
4:20 Effect of Etchant Composition and Silicon Crystal Orientation on Etch Rate
D. Yellowaga, J. Starzynski, B. Palmer, J. McFarland and S. Drews, Honeywell, US
4:40 Fabrication of Complex Diffractive Structures in an Organic-Inorganic Hybrid and Incorporation of Silver Nanoparticles
F.H. Scholes, F.L. Smith and S.A. Furman, CSIRO Manufacturing and Infrastructure Technology, AU
5:00 Fabrication of Nanochannels with Microfluidic Interface using PDMS Casting on Si/Ti Nanomold
M.J. Rust, S. Subramaniam and C.H. Ahn, University of Cincinnati, US
5:20 Direct Patterning of Functional Materials via Atmospheric-Pressure Ion Deposition
T.E. Hamedinger, T. Steindl, J. Albering, S. Rentenberger and R. Saf, Graz University of Technology, AU
 
 

Wednesday May 11

10:30 Nanodevices and Architectures - Sponsored by FreescaleSalon 1
 Session chair: David Ferry, Arizona State University, US
10:30 Emerging Nanoelectronic Devices and their Benchmarking Methodology
R. Chau, Intel, US
(speaker biography)
11:00 Room-Temperature InAlAs/InGaAs Planar Tunneling-coupled Transistor
J.S. Moon, R. Rajavel, D. Chow, S. Bui and D. Wong, HRL Labs, US
11:20 Polymeric Nanowire Architectures and Nanodevices
H. Liu, J. Kameoka, S. Verbridge and H.G. Craighead, Cornell University, US
11:40 Three-Dimensional Logic Architecture by Four-terminal Electrical Switches (FES) beyond Two-dimensional CMOS Architecture
S. Fujita, K. Abe and T.H. Lee, Stanford University, US
 
1:30 Self-Assembled Nanowires - Sponsored by FreescaleSalon 1
 Session chair: Roza Kotlyar, Intel, US
1:30 Semiconductor nanowires for future nanoelectronics
L. Samuelson, Lund University/the Nanometer Structure Consortium, SE
2:00 Nanopillar Arrays with Superior Mechanical Strength and Optimal Spacing for High Sensitivity Biosensors
V. Anandan, Y.L. Rao and G. Zhang, University of Georgia, US
2:20 Growth of Carbon Nano-Structures in Ceramic Materials
C. Kufazvinei, R.W. Leahy, S.M. Lipson, W.J. Blau, F.C. Dillon, T.R. Spalding, M.A. Morris, J.D. Holmes, G. Allan and J. Patterson, Trinity College Dublin, IE
2:40 Growth and Characterization of GaAs/AlGaAs Core-Shell Nanowires and AlGaAs Nanotubes
J. Noborisaka, J. Motohisa, S. Hara and T. Fukui, Hokkaido University, JP
 
3:30 Quantum Wires and Transport - Sponsored by FreescaleSalon 1
 Session chair: Roger Lake, University if California Riverside, US
3:30 Model-based assessment of silicon nanowires for future technology applications
R. Kotlyar, Intel, US
4:00 Implementation of Separable Scattering Mechanisms in Three-Dimensional Quantum Mechanical Simulations of a Silicon Quantum Wire
M.J. Gilbert, R. Akis and D.K. Ferry, Arizona State University, US
4:20 Single-Crystal Nanowire Transistor for Logic and Memory Applications
B. Yu, L. Ye and M. Meyyappan, NASA Ames Research Center, US
 
 

Thursday May 12

8:30 Thursday KeynotesGrand Ballroom E-F
8:30 Electronics and Optoelectronics with Single Carbon Nanotubes
P. Avouris, IBM, US
 
10:30 Spins and Organic WiresSalon 1
10:30 Spin Manipulation in Semiconductors and Spintronic Ultrafast Nanodevices
A.M. Bratkovsky, Hewlett-Packard Laboratories, US
11:00 Electronic Transport Through Carbon Nanotubes Effect of Contacts, Topological Defects, Dopants and Chemisorbed Impurities
A. Maiti, J. Hoekstra, J. Andzelm, N. Govind, A. Ricca, A. Svizhenko, H. Mehrez and M.P. Anantram, Accelrys Inc., US
11:30 Spin Density Functional Theory Simulations of Quantum Point Contacts: An Investigation of Spin Filtering Effects
R. Akis and D.K. Ferry, Arizona State University, US
 
1:30 Nanowire Design and ApplicationsSalon 1
1:30 The Design of a Silicon Wire DRAM Cell for Very Dense DRAM Architectures
A. Bindal and K. Aflatooni, San Jose State University, US
1:50 Nanowire Sensors and Arrays for Chemical/Biomolecule Detection
M. Yun, C. Lee, R.P. Vasquez, K. Ramanathan, M.A. Bangar, W. Chen, A. Mulchandan and N.V. Myung, Jet Propulsion Laboratory, US
2:10 Accurate Interface Modeling in Self-Consistent Molecular Conductance Calculations
G. Speyer, R. Akis and D.K. Ferry, Arizona State University, US
 
4:00 CNT Based Devices: electronics and optoelectronicsSalon 1
 Session chair: Alexandre Bratkovski, Hewlett Packard, US
4:00 Using Ultra-long Nanotubes to Make Identical CNT FETs
Z. Yu, C. Rutherglen, S. Li and P.J. Burke, University of California, Irvine, US
4:20 Centimetre-Long Carbon Nanotubes from Ethanol Decomposition
L.X. Zheng, M.J. O'Connell, S.K. Doorn, X.Z. Liao, Y.H. Zhao, M.A. Hoffbauer, Q.X. Jia, D.E. Peterson, J. Liu and Y.T. Zhu, Los Alamos National Lab, US
4:40 Vertically Grown Coaxial Double Gate Carbon Nanotube Field Effect Transistors for Tera Level Integration
M. Pourfath, A. Gehring, B.H. Cheong, W.J. Park, H. Kosina and S. Selberherr, Vienna University of Technology, AT
5:00 Single-Walled Carbon Nanotubes with Small Diameter, Controlled Density and Defined Locations Produced from Catalyst-Containing Polymer Films
J. Lu, T.E. Kopley, M. Hueschen, N. Moll, J. Bai, D.Y.Q. Fu, J. Liu, D. Rider, I. Manners and M.A. Winnik, Agilent Technologies, US
5:20 The Effect of Source/Drain Extension Asymmetry on the Leakage Current of Ohmicly-contacted Carbon Nanotube FETs
K. Alam and R. Lake, University of California Riverside, US

Synopsis

Scaling of semiconductor devices has continued unabated for the past three decades, and will likely continue for the near future. However, at the end of this decade (ca. 2011), the nature of the silicon device is such that many alternative approaches are likely to be viable contenders.

Already, new materials (SOI, SiGe, strained Si) are used in current production, high-k dielectrics, fully metallic gates and more non-(Si, SiO2) are expected in the coming generations. In addition, low dimension structures such as Fin-FETS are being considered. See the presentations:

Yet, the International Technology Roadmap for Semiconductors does not identify logic devices beyond CMOS, which presents a unique opportunity for the research community to influence the future of technology. Consequently, this symposium will address the role of several prospective technologies in creating new device options in the post-2011 era (sub-10 nm equivalent technologies).

For more information, please contact Alex Demkov

Impacted Industries

  • Semiconductor
  • Electronics
  • Lithography
  • Nanoprocessing
  • Nanofabrication
  • Nanomaterials
  • Characterization
 
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