Three-Dimensional Logic Architecture by Four-terminal Electrical Switches (FES) beyond Two-dimensional CMOS Architecture
S. Fujita, K. Abe and T.H. Lee
Stanford University, US
three-dimensional, post-CMOS, memory, switching device, logic
The technology expected after the lithography limit to keep increasing the number of transistors is thought to be either use of new transistors such as CNT by bottom-up process or three-dimensional (3D) architecture. We have proposed a new concept of 3D architecture using four-terminal electrical switches (FES), which can replace CMOS logic without bottom-up process. FES can be realized by modifying two-terminal nonvolatile memory devices, such as solid electrolyte memory using chalcogenide, phase change memory or electrical mechanical CNT memory. Since pass transistor logic and NOT-logic is also possible, all kinds of CMOS logic can be built by 3D-stacked FES logic gates. Although switching speed of FES is slower than CMOS by over one order, extremely wider parallel data path due to 3D can be used than that for 2D-CMOS logic by more than two orders. Logic data can flow not only horizontally but also vertically in the case of 3D circuit of FES Also, FES logic acts as nonvolatile logic, which is much promising in terms of decreasing power consumption for LSI, since power supply can be shut down for non-operating logic blocks. Thus 3D FES logic architecture has strong possibility to become superior to CMOS logic in future.
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Nanotech 2005 Conference Program Abstract