A Unified Compact Model for Electrostatic Discharge Protection Device Simulation
H-M Chou, Y-Y Cho, J-W Lee and Y. Li
National Chiao Tung University, TW
modeling, ESD, whole chip simulation
In modern microelectronics manufacturing, whole chip electrostatic discharge (ESD) protection circuit design is necessary for obtaining robust electrical performance [1-5]. In designing the whole chip ESD protection circuit, owing to its high circuit complexity, an efficient computer aided design (CAD) tool is not only helpful but also essential. Several ESD models for MOSFET or SCR devices, shown in Figs. 1 and 2, have been proposed; unfortunately, they are only constructed upon very simplified bipolar junction transistor (BJT) models. The major problem of those conventional BJTbased ESD models are caused from the fact that BJT models can only describe device behavior under the normally operation region but not in the ESD region. We in this paper propose a novel ESD model with very simple circuit equations and limited physical parameters. The developed ESD model is basically developed upon the device physics where the parasitic BJT will breakdown under the ESD stress. According to the mechanism shown in Fig. 3, we can simply formulate the snapback currentvoltage (IV) characteristics by using a current controlled voltage source (i.e., the breakdown voltage of parasitic BJT), the series resistance caused by drain side, and the external resistance Rx resulted from measurement instruments. In our model, Rx reflects the impedance of transmission line which is equal to 50ohm. This approach enables us to simulate the whole chip ESD robustness effectively. In the unified formulation, the MOSFET and SCR devices are considered used for the characterization. The device structure of the MOSFET and SCR devices are shown in Figs. 1 and 2. We compare the modeled and the measured snapback characteristics of the MOSFET device in Fig. 4 and the SCR devices from the Fig. 5 to Fig. 9. It is found that our model precisely describes the snapback behavior of both the MOSFET and SCR devices under ESD events. They demonstrate that our model successfully achieves four major ESD features: the trigger-on voltage, the snapback slope, the holding voltage, and the turn-on resistance. Among these results, we also evaluate the convergence property of the entire parameter range; after a comprehensive investigation, no singular point can be found. Here, we can conclude that our model is robust for whole chip ESD simulation. This work is supported in part by the National Science Council of TAIWAN under contracts NSC-93-2215-E-429-008 and NSC 93-2752-E-009-002-PAE, the grant of the Ministry of Economic Affairs, Taiwan under contract No. 92-EC-17-A-07-S1-0011, the grant from the Toppoly optoelectronics Corp. Miao-Li County, Taiwan during 2003-2004, and the grant from Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan in 2004.
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