Impact of Multi-Trap Assisted Tunneling on Gate Leakage of CMOS Memory Devices
R. Entner, A. Gehring, H. Kosina, T. Grasser and S. Selberherr
CMOS, memory, dielectric, modeling, multi-trap assisted tunneling
In this work a new approach for modeling gate leakage currents for memory cells which are highly degraded is proposed. In thicker dielectrics which are subject to high field stress and can therefore have a high defect density, not only direct tunneling currents but also trap-assisted tunneling plays an important role. By rigorous simulation we show, for the first time, that also a multi-trap assisted tunneling component becomes important for dielectric thicknesses above approximately 3 nm and even gains importance for thicker layers.
Back to Program
Nanotech 2005 Conference Program Abstract