Airgap and Line Slope Modeling for Interconnect
F. Badrieh and H. Puchner
Cypress Semiconductor, US
interconnect, airgaps, voids, field solver, line slope, backend, modeling, capacitance
We have devised a generic methodology for characterizing airgaps and line slope and including those features in interconnect modeling. The method is silicon-based and can be used to accurately model the impact on capacitance. Our main conclusion is that airgaps result in a significant reduction in capacitance at smaller space. Metal slope on the other hand kick in at moderate-to-large space and results in an increase in capacitance.
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Nanotech 2005 Conference Program Abstract