A Nanocore/CMOS Hybrid System-on-Package (SoP) Architecture for Future Nanoelectronic Systems
R. Weerasekera, J. Liu, L-R Zheng and H. Tenhunen
CMOS/nano, tera-scale, nanosystems
We propose Autonomous Error-Tolerant (AET) cellular network based architecture for future nano-electronic systems. Each AET cell consists of a nano-core, dedicated for local computing, CMOS cell-peripherals, responsible for cell I/O and System-level tasks, and their interface circuits. Since nano-devices are lack of significant voltage gain and the nano-interconnetcs are highly resistive, driving signals for a long distance is hard to achieve. Apart from these, fabricating nano-interconnects need high precise patterning technologies. So, we propose, for inter-cellular communication, CMOS interconnects in 45 nm feature size, with a sufficient bandwidth as required.
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Nanotech 2005 Conference Program Abstract