Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics
T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, E. Suzuki and H. Koike
National Institute of Advanced Industrial Science and Technology (AIST), JP
FET, double-gate, compact-model, short-channel
We have proposed a compact model of the DG MOSFETs which handles two gates independently. The model can simulate the DG MOSFETs of asymmetric gate design, together with their four-terminal operation. In this report, we present a compact model that includes a complete mobility modeling, and discuss several points which are specific to ultra-short channel DG MOSFETs. In DG MOSFETs there are many aspects different from conventional MOSFETs such as sandwiched structures, source/drain region without pn junctions, a different approach for gate-overlap design, and floating body. These aspects should be reflected to the model design. We first discuss on the formation of a mobility model, starting from the bulk mobility, modulating according to the universal curve, adding roughness scattering inversely proportional to the channel thickness which is always present in the case of DG MOSFET. The results are compared with the device simulator results. We further discuss on the short channel effect, which is small compared to that of conventional FETs, but appears in a different way. We will comment on the quantum size effect and dopant tailing effect on the designing of the compact model.
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Nanotech 2005 Conference Program Abstract