The Design of a Silicon Wire DRAM Cell for Very Dense DRAM Architectures
A. Bindal and K. Aflatooni
San Jose State University, US
Keywords:
DRAM, nano wire, silicon wire, vertical FET
Abstract:
In this study, we propose a new DRAM cell that uses a silicon-wire pass transistor stacked on top of a high-dielectric capacitor rated of holding industry-standard 32 fCoulomb charge. We show that the performance of the transistor and the characteristics of the DRAM cell are comparable with those reported in the literature.
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Nanotech 2005 Conference Program Abstract
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