CMOS Architectures for NOR & NAND Logic Gates Using Single Electron Transistors
A. Venkataratnam and A.K. Goel
Michigan Technological University, US
single electron transistors, CMOS, logic devices
Single electron transistor is one of the nano devices suitable for developing nano-scale logic circuits. In this paper, CMOS architectures for NOR and NAND gates have been proposed and their operational characteristics have been verified by using the simulation tools such as SIMON and SET-SPICE. First, a two-input NOR gate was designed and verified and then the design was extended to implement a NOR3 gate and a NAND2 gate. The basic layout of an SET is a small conducting island coupled to the source and drain leads by tunnel junctions that are capacitively coupled to a control gate and one or more input gates. Operation of an SET as an “n” and a “p” device was achieved by controlling the charge on the SET island. This charge is related to the capacitance at the island, capacitance at the gate electrode and the voltage applied to the gate. The effects of temperature, island capacitance and the ability of the proposed gate to drive load capacitance have also been studied. The proposed CMOS based designs will lead to easy portability of other CMOS-based circuit designs to SET-based logic circuits. This will help in reducing the time to market of logic circuits based on this upcoming nano device technology.
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