Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices
J. Watts, N. Lu, C. Bittner, S. Grundon and J. Oppold
FET variation modeling, circuit design, layout choices, compact modeling
In addition to the overall range of circuit characteristics expected from process variation the circuit designer needs to know how closely different circuit element will track one another. We describe a new methodology for modeling correlation between the chip mean variation different design FET and between different FET instances on a single chip. In addition it enables modeling the impact of circuit design choices on FET and circuit tracking.
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Nanotech 2005 Conference Program Abstract