Analytical Surface Potential Model with Polysilicon Gate Depletion Effect for NMOS
E. Cumberbatch, H. Abebe, H. Morris and V. Tyree
USC/ISI MOSIS, US
device modeling, MOSFET, polysilicon gate depletion, SPICE, surface potential
Different modeling approaches for the sub-100nm MOSFET are discussed in  and the surface potential description model is reported to be promising, [1, 2]. Surface potential changes impact gate capacitance and current-voltage (I-V) characteristics of the MOS device at thin gate oxides (below 4nm.) The surface potential model is usually obtained by solving the Poisson equation with boundary conditions. The major drawback of this approach is that the surface potential is given by an implicit relation and can only be solved iteratively, requiring expensive computational time. For circuit analysis application, analytical, explicit solutions are preferred because of their simplicity and computational speed. Here we present an analytical model for the polysilicon (poly) gate depletion effect on the surface potential of the NMOS device. The reduction of the channel surface potential due to poly depletion is expressed in terms of the doping concentration on both sides of the gate oxide and the oxide thickness. The surface potential model is derived by directly solving the Poisson equation on the poly and silicon sides using asymptotic methods, , and the final analytical model exhibits an excellent fit with numerical data (see Figures 1 and 2.) We believe that these models will be very useful in improving SPICE circuit simulations in advanced VLSI since the gate depletion effect is significant in nanoscale MOSFET devices.
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Nanotech 2005 Conference Program Abstract