Semiconductor nanowires for future nanoelectronics

Keywords:
nanowires, one-dimensional, heterostructures, nanoelectronics

Abstract:
Guided self-assembly for bottom-up fabrication of semiconductor semiconductor nanowires has become a promising route to further shrink and make more efficient routes for fabrication of nanoelectronic devices and circuits [1]. I will in this talk describe mechanisms for the growth of nanowires [2, 3] containing designed heterostructures, primarily based on lithographically defined metal catalysts to induce growth [4, 5]. Examples will be given of one-dimensional nanoelectronic devices where tunnel-barriers are formed inside nanowires such that electrons are controllably tunneling into and out from quantum dots, allowing resonant tunneling devices as well as single-electron transistors to be studied [6, 7]. In the limit of extremely small quantum dots, the sequential filling of atomic-like levels can be spectroscopically probed and investigated [8]. Of special significance for successful usage of the technology will be recently demonstrated ability to epitaxially form III-V nanowires on silicon substrates, hence permitting advanced heterostructure devices for electronics as well as photonics to be implemented on a silicon platform [9, 10].

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Nanotech 2005 Conference Program Abstract