Nano Science and Technology InstituteNano Science and Technology Institute
Nano Science and Technology Institute 2005 NSTI Nanotechnology Conference & Trade Show
Nanotech 2005
Bio Nano 2005
Business & Investment
Nano Impact Workshop
Program
Sessions
Sunday
Monday
Tuesday
Wednesday
Thursday
Index of Authors
Index of Keywords
Keynote Presentations
Confirmed Speakers
Participating Companies
Industry Focus Sessions
Nanotech Expo
Special Symposia
Conferences
Sponsors
Exhibitors
Venue 2005
Organization
Press Room
Subscribe
Site Map
 
Nanotech 2005 At A Glance
Nanotech Proceedings
Nanotechnology Proceedings
Global Partner
nano tech
Supporting Organizations
Nanotech 2005 Supporting Organization
Media Sponsors
Nanotech 2005 Medias Sponsors
Event Contact
696 San Ramon Valley Blvd., Ste. 423
Danville, CA 94526
Ph: (925) 353-5004
Fx: (925) 886-8461
E-mail:
 
 

Mismatch Improvement with XMOS Structure

P.B.Y. Tan, A.V. Kordesch and O. Sidek
Silterra Malaysia Sdn Bhd, MY

Keywords:
mismatch, matching, XMOS, MOS, transistor performance

Abstract:
MOS transistor has been continuously scaled down to improve the device performance. Smaller MOS transistors have higher transconductance (gm) and low capacitance, so the ratio gm/C is improved by shrinking. Shorter gate length provides higher drain current which improve the transistor switching speed. Mismatch is one of the major barrier for device downscaling, especially for analog designers. Mismatch and transistor size always contradict each others. According to inverse square root area law, mismatch increases when transistor size decreases. This means that it is almost impossible to improve the transistor performance (by shrinking the gate length) and to improve the transistor mismatch at the same time. In this paper, we propose a method of constructing the gate structure that will improve both the transistor performance and the transistor mismatch at the same time. The structure that we proposed is Cross MOS (XMOS) structure. The XMOS structure has a cross gate that provide extra channel width and extra gate area that gives higher transistor performance and better transistor matching. But no increase in source/drain parasitic capacitance.

Back to Program

Sessions Sunday Monday Tuesday Wednesday Thursday Authors

Nanotech 2005 Conference Program Abstract

 
Gold Sponsors
Nanotech Gold Sponsors
Silver Sponsors
Nanotech Silver Sponsors
Gold Key Sponsors
Nanotech Gold Key Sponsors
Nanotech Ventures Sponsors
Nanotech Ventures Sponsors
Sponsors
Nanotech Sponsors
News Headlines
NSTI Online Community
 
 

© Nano Science and Technology Institute, all rights reserved.
Terms of use | Privacy policy | Contact