How To Design for Analog Yield using Monte Carlo Mismatch SPICE Models
P.B.Y. Tan, A.V. Kordesch and O. Sidek
Silterra Malaysia Sdn Bhd, MY
mismatch, yield, Monte Carlo, SPICE, analog
The downscaling of devices causes the unpredictability of analog circuit yield. Transistor mismatch is one of the obstacles to achieving high yield. Analog circuit designers usually run Monte Carlo mismatch models to predict the functionality of their circuits especially when minimum size devices are used. As per inverse square root law, mismatch becomes more severe when transistor gate area decreases. In this work we demonstrate a method that analog circuit designers can use to predict the circuit yield. We propose a simple way to predict analog circuit yield by using a combination of Monte Carlo mismatch and process variation SPICE models. If only process variation were used, there would be no mismatch or offset voltage. If only mismatch models were used, then there would be no process variation. We demonstrate the yield prediction simulation by using Silterra 0.18um MOS SPICE models. We use a differential matched pair as a simple analog circuit example. In our example, offset voltage (VOS) is used as the circuit performance parameter. The yielding circuits will have to meet the requirement that VOS < 10 mV. We show how to find the minimum matched transistor width required to achieve 3-sigma yield (99.7%). The proposed method is as follows: Start with the set of required performance parameters for the circuit and their specifications. As a simple example we use a differential pair with performance parameters: DC gain (A), offset voltage (VOS), and power supply rejection ratio (PSRR). Our goal is to select values for the circuit design parameters (L, W, R) such that the predicted yield for this circuit will meet expectations, say 99.7%. In our example, we run Monte Carlo SPICE simulations with N = 50. The SPICE models from the manufacturer already contain the statistical variations of the manufacturing process in the form of Monte Carlo coefficients. Our simulation includes both process variation and mismatch. From this result we plot 3-sigma VOS versus the design parameter W as shown in Figure1. To achieve VOS of 10 mV we see that the required W is at least 3.5 um. This example illustrates how we used Monte Carlo SPICE models to design for 99.7% yield (3-sigma). The aim of this paper is to illustrate usage of mismatch models not only for yield prediction but for designing a circuit to achieve a given yield target. The method shown in this paper will enable analog circuit designers to take into account the trade-off between matched transistors size and yield when designing their circuits. We hope this paper will give designers an insight into their circuit’s yield caused by transistor mismatch and process variation before going into fabrication.
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