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Wafer Scale Aligned Sub-25nm Metal Nanowires on Silicon (110) using PEDAL Lift-off Process

S.R. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson and P.D. Franzon
North Carolina State University, US

Keywords:
nanotechnology, nanowires, nanoimprinting

Abstract:
We have demonstrated a new PEDAL process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by doing shadow metalization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of Silicon nitride and crystallized a-Silicon. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer shipley1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of aligned nanowires template. After doing shadow metallization of required metal we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the Logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques.

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