|Certain circuits can only be simulated accurately using the new approach, known as the PSP model, including passive mixers used in mobile phones to increase battery life and current-ratio based circuits used in analog to digital converters.|
In addition, PSP has better RF capabilities than the existing models and accurately predicts transistor behavior up to frequencies well above 50 GHz.
Dr. Gennady Gildenblat, professor of electrical engineering, leads PSP development at Penn State. He says, “Fabricating integrated circuits is expensive and improving them by trial and error adds significantly to that expense. Accurate models that provide detailed mathematical descriptions offer engineers the chance to do science-based engineering and to get it right the first time.” Gildenblat will detail PSP in an invited talk, “Introduction to PSP MOSFET Model, ” at the Nanotech 2005 International Conference, May 10, in Anaheim, Ca. His co-authors are X. Li, H. Wang and W. Wu, electrical engineering graduate students at Penn State, and R. van Langevelde, A. J. Scholten, G. D. J. Smit and D. B. M. Klaassen, Philips Research Laboratories, The Netherlands.
The key variable in the PSP model is surface potential at the interface between the silicon and silicon dioxide in the transistor. Since PSP is based on this physical variable, it yields better predictions of the behavior of integrated circuits than is possible with alternative models, especially when devices are miniaturized or are operated at their limits, the developers say.
Models, such as PSP, which describe transistors in a mathematical way, are used in circuit simulators. For example, PSP has been tested on a simulation of a passive mixer, a surprisingly difficult problem that Gildenblat and others only accomplished recently. In addition, PSP has been verified against measurements on transistors from various manufacturers, including those made with the latest technology.
All details of the PSP model are being made available on the Internet. Philips SIMKit software allows PSP to be directly coupled to many popular circuit simulators.
Speaking of the Penn State/Philips collaboration, Dr. Dirk Klaassen, research fellow at Philips Research, says, “Our cooperation brings together the best fundamental academic and pragmatic industrial knowledge and expertise on compact modeling. It directly ties our combined deep understanding of the physical behavior of MOS transistors onto the requirements set by IC designers and the application areas most relevant to them.”
PSP is being submitted to the Compact Model Council (CMC) as a candidate for standardization. The Council represents 27 major semiconductor companies that use models. The Council chooses candidates for standardization based on the technical needs of its members. The CMC is scheduled to select a new model for CMOS transistors later this year.
PSP development was supported, in part, at Penn State by the Semiconductor Research Corporation, the Motorola Shared University Partnership Program, the IBM University Partnership Award, Freescale Semiconductor, and LSI Logic. The development at Philips Research was supported by the EU Projects IMPACT and NanoCMOS.